"By Walt Jung, ADI
The sample and hold (s / h) function is the basis of data acquisition and analog-to-digital conversion. The S / h amplifier circuit has two different basic working states. In the first state, the input signal is sampled and transmitted to the output (sampling). In the second state, the last sample value (hold) is maintained until the input is sampled again. In most applications, S / h is used as the "front end" of analog-to-digital converter in data acquisition system. When used in this way, S / h is mainly used to keep the analog input voltage level constant during the time period required to perform analog-to-digital conversion.
Specifically, S / h is a system function module that the data conversion system must have. The analog-to-digital converter used must provide constant and accurate analog input during conversion. Successive approximation type analog-to-digital converter is an example of this usage. Ideally, S / h will "freeze" the last instantaneous input voltage before receiving the hold command, and supply the voltage to the analog-to-digital converter as it is, and then the analog-to-digital converter will convert the voltage into the corresponding digital word. In fact, many error factors will be involved in the implementation of S / h. Therefore, this application note will explore these basic considerations, as well as representative device topologies and applications.
Basic operation of S / h amplifier
Fig. 1 shows some basic information of S / h, and Fig. 1a is a basic s / H circuit structure. The figure shows that the analog input signal to be digitized is directly transmitted to the electronic switch S1. According to the state of S1, the signal will be transmitted to the holding capacitor ch or intercepted. The state of switch S1 is controlled by the S / h control line, which is a digital input.
When S1 is off, the input signal transmitted to ch is buffered by A1. The signal may also be transmitted to the S / h output (the possible impact of low-pass filter is not considered in this discussion). If S1 remains connected for a period of time during an input change (like an AC waveform), this operation can also be called tracking; That is, any input changes are transmitted to the output.
a. The basic s / H circuit consists of switch, holding capacitor and buffer amplifier
b. S / h waveform, showing the sampled input (top), S / h control (middle) and S / h output (bottom)
Figure 1. S / h basic information
When S1 is turned on, the last input voltage value is retained on ch as charge; That is, keep the voltage constant. A1 continues to read the voltage until the next sampling cycle is entered. Figure 1b shows this operation through input, output and control waveforms. S / H circuit is used to realize various signal processing functions; It can be used not only to realize analog-to-digital interface, but also to realize more general analog memory functions, such as self stabilizing zero amplifier.
The S / h operating waveform shown in Fig. 1b is almost ideal, assuming that the switching, tracking, holding characteristics and load / source immunity are ideal. However, in fact, there are s / h errors in each state (four states) of the device. These states include:
(1) Hold sample conversion
(2) Sampling interval
(3) Sample and hold conversion
(4) Keep interval
Sample / track and hold amplifier
Obviously, these errors may be very important for many applications, but they are all important for high-precision applications (10 bits, or accuracy of 0.1% or less). Specific definitions and descriptions are described below.
Hold sample conversion error
When the device switches from the hold state to the sampling state, these errors are related to the time interval. Since the input may have changed greatly since the last sampling voltage (for example, it may be full scale), the S / h must re acquire the input signal and stabilize within its rated accuracy range again. As shown in Figure 2.
Acquisition time is the time required for S / h to collect and track the input signal after receiving the sampling command. It is usually specified as a full-scale level change (- 10V to + 10V, and vice versa) because this represents the worst case of the time required to obtain a signal at any level. The output must assume that the required level is within the rated error range, consistent with the accuracy level required for conversion or sampling. For example, it may be 0.01% or 0.1%. Fig. 2A shows a hold sampling acquisition waveform.
Figure 2A. Hold sampling node acquisition time, showing new signal acquisition (top) and S / h control (bottom)
For large amplitude hold sampling changes, most of the acquisition time is the initial swing interval. After this high error interval, the output may overshoot and then stabilize within ± 2mV rated accuracy; Taking 20V scale as an example, the range is ± 0.01%. Note that when the signal is stable and maintained within the rated error range, the acquisition time ends.
Acquisition time is not only the main component of maintaining sampling error, but also the main factor determining the working speed of S / H part of the conversion system. The typical time is about a few milliseconds to an accuracy of 0.1% or 0.01% or higher. The acquisition time depends largely on the value of the holding capacitance used, which (usually) affects the slew rate.
Fig. 2B shows the hold sampling transient, that is, the switching transient generated when switching from the hold mode to the sampling mode. Note that this transient occurs even if there is little difference between the previous holding voltage and the new sample. Since the magnitude of this transient may far exceed the S / h rated accuracy (possibly up to several hundred millivolts), sufficient time must be allowed for this transient to disappear before determining that the output voltage sample is valid.
Figure 2B. Hold sampling mode transient and setup time
Since the establishment time of the transient will continue after the start of the hold sampling command, the system timing must allow this. However, in practice, the establishment time associated with holding sampling transients is usually much shorter than the acquisition time. Therefore, the time interval equivalent to the worst case (or acquisition time) usually automatically considers the hold sampling transient error and its related establishment time.
Sampling error
During the sampling interval, the S / h device tracks the input signal like an operational amplifier. In fact, most s / h devices are either special operational amplifiers or built using operational amplifiers whose characteristics are very suitable for S / h. Therefore, since most s / h amplifiers will be reduced to or equivalent to operational amplifier voltage followers or inverters, similar methods can be used to calculate their sampling mode errors.
Pure proportional errors in S / h can usually be regarded as benign errors because they can be largely eliminated by calibration adjustment. Generally, to perform this operation, the analog-to-digital reference source is a very convenient point, so that all system proportional errors can be eliminated at one time. Of course, this method is suitable for traditional usage, such as an analog-to-digital converter and an S / h. If there are multiple s / h before the analog-to-digital converter, or if the S / h is only a part of other circuits, the local gain needs to be adjusted through the gain proportional resistance.
In any case, the deviation between the worst case and the ideal s / h scale factor must be understood and taken into account when calculating the error budget. In general, the scale factor is an error of 1 ± 0.001% or less. That is, the type of gain error associated with the voltage follower connection.
When a gain resistor is used, for example, when s / h is used for in-phase gain rather than unit gain, the resistance tolerance will significantly increase this error. For inverting mode operation s / h, in any case, a gain proportional resistor must be used. In either case, it is very advantageous to install application resistors on S / h chip, because they will obtain higher preset accuracy and maximum offset specifications. For devices, the recent trend is to use preset resistors to support common gains - 1, + 2, etc.
Note that although the actual gain (proportional) error can be adjusted by system proportional calibration, gain nonlinearity is not equivalent to non adjustable error.
Gain nonlinearity is a critical s / h error, which is shown as the deviation from the ideal transmission characteristics. This error component is the dynamic deviation between the device and the ideal s / h gain value (such as + 1, + 2, - 1, - 2, etc.) when the device operates within its rated signal output range (usually ± 10V). The maximum error component is usually the input stage common mode error, which is a typical case (generally the most common) in the follower type connection. In the inverter type connection, the common mode error disappears, but the resistance matching error will become the error source.
The typical value of S / h nonlinearity is 0.001% to 0.01% in the range of ± 10V signal. Obviously, in order to maintain the system performance, the S / h nonlinearity must be better than the overall nonlinearity established by the analog-to-digital converter used. For S / h nonlinearity, a good rule can be followed: the value should be one order of magnitude higher than the basic resolution of the converter. For example, an S / h nonlinearity of 0.01% or better is used with a 10 bit converter. Note that the user may need to calculate the nonlinearity according to the common mode rejection ratio (CMRR) of S / h, for example, 80dB CMRR is equivalent to 0.01% nonlinearity.
Offset refers to the DC offset between the input and output when the S / h input is grounded. It is usually adjusted to zero by an optional trim potentiometer. Typical DC bias specifications are ± 2mV or less. For S / h applications, its own pure offset is not a problem, because it can always be adjusted to zero during the overall calibration of the system. The fine-tuning and calibration of analog-to-digital converter can also be completed manually or through software.
Offset temperature drift is another matter because it is difficult to distinguish it from the actual signal. Unless the self stable zero calibration period is included, the S / h offset drift error component cannot be reduced and will produce errors with temperature changes. The typical value of S / h drift is 1 to 10 µ V / ° C. whether it requires higher accuracy or a wide temperature range, this error is a serious error.
The S / h offset voltage also varies with the supply voltage, which should also be explained. Generally, the power supply rejection is about 80dB or 100 µ V / v. This parameter is usually less important for a well regulated power supply or when using an automatic calibration cycle.
The establishment time is suitable for the sampling mode with rapid change of input voltage. When tracking the input signal, the S / h is dynamically limited, which is similar to other operational amplifier configurations.
The setup time is determined by the slew rate and small signal bandwidth. If the step size changes greatly, the slew rate is the main reason. The typical slew rate is 5 to 10V / µ s and the establishment time is 5-10 µ s. As mentioned in the acquisition time section, the exact specification depends largely on the holding capacitance.
Sample and hold conversion error
Aperture time or aperture delay refers to the time from issuing the hold command to actually opening the S / h switch. For the rapidly changing input voltage, an error will occur in the process of determining the actual holding voltage. The resulting voltage error will be equal to the change in input voltage during the effective aperture time interval.
Fig. 3 generally shows the error related to the aperture time, and Fig. 3A shows how the aperture delay generates an error within the holding voltage. For the rapidly changing input voltage, the S / h voltage changes in an amplitude close to 1 / 2lsb during the switch from on to off.
Figure 3a. Time / voltage error related to aperture. Analog input / output (top), sample / hold drive (bottom).
As a general example of the influence of aperture time, consider the input signal sampled at 10ns aperture time with a change rate (signal slope) of 1 V / µ s. Due to the DV / dt error related to aperture time, this will produce a 10mV sampling error.
This error is usually serious. The effective aperture delay can be compensated by executing the hold command in the system in advance according to the nominal aperture delay duration, but this is not all error.
After removing the nominal aperture delay, the remaining error is called aperture jitter (or uncertainty). It has a high signal slope input, which is the factor that really limits the S / h sampling error. Aperture jitter refers to the net change in the actual s / h switching timing between samples. This jitter ultimately limits the aperture time-dependent error. For the 1V / µ s slew rate example, 1ns aperture jitter will lead to ± 1mV voltage uncertainty.
The general relationship between the limiting aperture time and the resulting allowable full-scale level sine wave input frequency can be graphically displayed. As shown in Figure 3B. This figure is based on the maximum (full scale) sine wave input frequency with an error of no more than 1 / 2lsb. The frequency Fmax is calculated as follows:
Figure 3b. maximum full range input sine wave frequency (Fmax) at various aperture times and resolutions
Where π = 3.14, Ta is the limited aperture time, and "n" is the resolution of the converter (unit: bit).
Since these data are for limited aperture, they can be used for analog-to-digital converter with S / h or separate analog-to-digital converter operation. In the latter case, the analog-to-digital conversion time defines the effective aperture time.
This data clearly shows the value of S / h used to maximize the allowable input frequency. The maximum output frequency supported by the 10 µ s 8-bit analog-to-digital converter without s / h is about 60Hz. On the other hand, when using S / h with an aperture time of only 100 ns, the same analog-to-digital converter supports a maximum frequency of 6 kHz. Note that there is a more general relationship; As the conversion resolution increases, Fmax decreases within a given conversion time. Therefore, when the resolution or frequency increases, the demand for S / h becomes more critical.
Obviously, the shorter the aperture time in S / h, the better, because this will cause less restrictions on the analog-to-digital converter used together. The time quoted in the description is very typical for medium speed IC. The S / H circuit is not the final factor limiting the system timing, because the maximum throughput frequency usually occurs before the aperture time limit frequency.
S / h offset (also known as S / h "base", "jump" or "step") is the simulation error caused by transient charge when s / h performs sample and hold conversion. It is caused by the limited capacitance of the S / h switch used and, to a lesser extent, by the layout and / or package capacitance. These capacitors are directly fed to the holding capacitor through a part of the digital control signal. In general, since the parasitic coupling capacitance is fixed in a given device and layout, this error can be reduced by using a larger holding capacitance. Figure 4 shows this effect.
Figure 4. Sample hold offset (top), S / h control (bottom)
This error may be several MV, and in some cases, it can be compensated by feeding the inverse control signal to the holding capacitor with a small external coupling capacitor. In general, this error can be reduced by reducing the peak to peak level of the digital control signal to an absolute minimum and by shielding / protecting the coupling path between the signal and the ch node.
Note that the sample and hold offset is not always specified directly in this way, especially in IC devices using external hold capacitors. In this case, the technical specification of charge will be given, in PC. In these cases, the S / h offset can be calculated using the following formula:
For example, 10pc charge transfer using 1000pf ch will result in 10mV
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