"I. phase I, no modification
2、 Phase II
u-boot-1.3.4\lib_ arm\board.c
1. Add header file
2. Add version number
3.start_ Initialization part of armboot
Board level initialization part init_ sequence->board_ init
3.1 create a new board resource header file, include \ ASM arm \ arch-at91sam9 \ at91sam9m10g45ek. H (address and interrupt number)
Document writing ideas:
1. Refer to the AT91SAM9263. H file of the same series of chips
2. Peripheral identifier
3. Outdoor enclosure physical base address
4. Physical base address of system peripherals (based on system control register)
5. Internal storage base address
Refer to chart:
Attach source code:
at91sam9m10g45ek.h
3.2 create the board bus matrix header file include \ ASM arm \ arch-at91sam9 \ at91sam9g45_ Matrix. H (address)
Document writing ideas:
1. Refer to AT91SAM9263 of the same series of chips_ Matrix. H file
2. Register mapping table
Refer to chart:
Attach source code:
at91sam9g45_ matrix.h
3.3 create the board initialization file u-boot-1.3.4 / board / ATMEL / at91sam9m10g45ek / at91sam9m10g45ek. C
Document writing ideas:
1) Refer to the at91sam9263ek. C file of the same series of chips
2) Initialize board in queue_ init()
2.1) console initialization
2.2) machine ID initialization
2.3) start parameter storage address initialization
2.4) serial port hardware initialization
2.4.1) set the multiplex GPIO port as a device
2.4.2) write register to enable clock on (parameter is peripheral identifier)
2.5) nandflash hardware initialization
2.5.1) read chip selection register
2.5.2) set EBI chip selection 3 to assign to static storage controller
2.5.3) set the static storage controller
2.5.4) peripheral clock on register, parallel IO controller C
2.5.5) C8 initialization as input
2.5.6) C14 is initialized to output
2.6) SPI hardware initialization
2.6.1) set B3 as the multiplexed GPIO port B device and use it as npcs0
2.6.2) set B0 as the multiplexed GPIO port B device and use it as miso0
2.6.3) set B1 as multiplexed GPIO port B device, which is used as mosi0
2.6.4) set B2 as the multiplexed GPIO port B device and use it as spck0
2.6.5) Write register, enable clock on (parameter is peripheral identifier spi0)
2.7) MACB hardware initialization
2.7.1) it is forbidden to pull up A15, A12 and A13
2.7.2) Read reset register mode
2.7.3) set the reset register cycle to allow reset
2.7.4) set external reset
2.7.5) wait for hardware reset to complete
2.7.6) setting allowed reset
2.7.7) enable pull-up A15 A12 A13
2.7.8) Multiplexed IO a10-19 is a device function: etxck_ EREFCK、ERXDV、ERX0、ERX1、ERXER、ETXEN、ETX0、ETX1、EMDIO、EMDC
2.7.9) Multiplexed IO a6-9 and a27-30 are equipment B functions: ECRs, ecol, erx2, erx3, erxck, etx2, etx3, etxer
2.7.10) D5 pin reset
2.8) LCD hardware initialization
2.8.1) Multiplexed IO E0 e4-30 is a device function: lcddpwr, lcdhsync, lcddotck, lcdden, lcdd0-23
2.8.1) Peripheral clock on register, LCD
3) Initialize DRAM in queue_ init()
3.1) initialization ram start address 0x70000000
3.2) initialization ram size 0x0800000
Attach source code:
1 #include 2 #include 3 #include 4 #include 5 #include 6 #include 7 #include 8 #include 9 #include 10 #include 11 //#include //have udelay() 12 #include 13 #if defined(CONFIG_ RESET_ PHY_ R) && defined(CONFIG_ MACB) 14 #include 15 #endif 16 17 DECLARE_ GLOBAL_ DATA_ PTR; 18 19 /* ------------------------------------------------------------------------- */ 20 /* 21 * Miscelaneous platform dependent initialisaTIons 22 */ 23 24 staTIc void at91samm10g45ek_ serial_ hw_ init(void) 25 { 26 #ifdef CONFIG_ USART0 27 at91_ set_ A_ periph(AT91_ PIN_ PB19, 1); /* TXD0 */ 28 at91_ set_ A_ periph(AT91_ PIN_ PB18, 0); /* RXD0 */ 29 at91_ sys_ write(AT91_ PMC_ PCER, 1 << AT91SAM9G45_ ID_ US0); 30 #endif 31 32 #ifdef CONFIG_ USART1 33 at91_ set_ A_ periph(AT91_ PIN_ PB4, 1); /* TXD1 */ 34 at91_ set_ A_ periph(AT91_ PIN_ PB5, 0); /* RXD1 */ 35 at91_ sys_ write(AT91_ PMC_ PCER, 1 << AT91SAM9G45_ ID_ US1); 36 #endif 37 38 #ifdef CONFIG_ USART2 39 at91_ set_ A_ periph(AT91_ PIN_ PD6, 1); /* TXD2 */ 40 at91_ set_ A_ periph(AT91_ PIN_ PD7, 0); /* RXD2 */ 41 at91_ sys_ write(AT91_ PMC_ PCER, 1 << AT91SAM9G45_ ID_ US2); 42 #endif 43 44 #ifdef CONFIG_ USART3 /* DBGU */ 45 at91_ set_ A_ periph(AT91_ PIN_ PB12, 0); /* DRXD */ 46 at91_ set_ A_ periph(AT91_ PIN_ PB13, 1); /* DTXD */ 47 at91_ sys_ write(AT91_ PMC_ PCER, 1 << AT91_ ID_ SYS); 48 #endif 49 } 50 51 #ifdef CONFIG_ CMD_ NAND 52 staTIc void at91samm10g45ek_ nand_ hw_ init(void) 53 { 54 unsigned long csa; 55 56 / * enable CS3 * / 57 / / EBI chip selection 3 assigned to static storage controller 58 CSA = at91_ sys_ read(AT91_ MATRIX_ EBICSA); 59 at91_ sys_ write(AT91_ MATRIX_ EBICSA, csa | AT91_ MATRIX_ EBI_ CS3A_ SMC_ SMARTMEDIA); 60 61 / * configure SMC CS3 for NAND / SmartMedia * / 62 / / nwe setup time = (128 x nwe)_ SETUP[5] + NWE_ Setup [4:0]) clock cycle 63 / / NCS establishment duration = (128 x NCS_ WR_ SETUP[5] + NCS_ WR_ Setup [4:0]) clock cycle 64 / / NRD establishment duration = (128 x NRD_ SETUP[5] + NRD_ Setup [4:0]) clock cycle 65 / / NCS establishment duration = (128 x NCS_ RD_ SETUP[5] + NCS_ RD_ Setup [4:0]) clock cycle 66 at91_ sys_ write(AT91_ SMC_ SETUP(3), 67 AT91_ SMC_ NWESETUP_( 1) | AT91_ SMC_ NCS_ WRSETUP_( 0) | 68 AT91_ SMC_ NRDSETUP_( 1) | AT91_ SMC_ NCS_ RDSETUP_( 0)); 69 / / nwe pulse width = (256 x nwe)_ PULSE[6] + NWE_ Pulse [5:0]) clock cycle 70 / / NCS pulse width = (256 x NCS_ WR_ PULSE[6] + NCS_ WR_ Pulse [5:0]) clock cycle 71 / / NRD pulse width = (256 x NRD_ PULSE[6] + NRD_ Pulse [5:0]) clock cycle 72 / / NCS pulse width = (256 x NCS_ RD_ PULSE[6] + NCS_ RD_ Pulse [5:0]) clock cycle 73 at91_ sys_ write(AT91_ SMC_ PULSE(3), 74 AT91_ SMC_ NWEPULSE_( 4) | AT91_ SMC_ NCS_ WRPULSE_( 3) | 75 AT91_ SMC_ NRDPULSE_( 3) | AT91_ SMC_ NCS_ RDPULSE_( 2)); 76 / / write cycle length = (nwe)_ CYCLE[8:7] X 256 + NWE_ Cycle [6:0]) clock cycle 77 / / read cycle length = (NRD)_ CYCLE[8:7] X 256 + NRD_ Cycle [6:0]) clock cycle 78 at91_ sys_ write(AT91_ SMC_ CYCLE(3), 79 AT91_ SMC_ NWECYCLE_( 7) | AT91_ SMC_ NRDCYCLE_( 4)); 80 / / read operation is controlled by NRD signal. 81 / / the write operation is controlled by the nwe signal. 82 / / the nwait is used to extend the current read or write signal. It is only considered in the pulse width of the read and write control signals. If nwait is enabled, at least one cycle must be set in the read and write control signals. 83 / / data bus width 8-bit bus 84 / / data floating time: the integer cycle time for external devices to release data after reading the rising edge of the control signal 85 at91_ sys_ write(AT91_ SMC_ MODE(3), 86 AT91_ SMC_ READMODE | AT91_ SMC_ WRITEMODE | 87 AT91_ SMC_ EXNWMODE_ DISABLE | 88 #ifdef CFG_ NAND_ DBW_ 16 89 AT91_ SMC_ DBW_ 16 | 90 #else /* CFG_ NAND_ DBW_ 8 */ 91 AT91_ SMC_ DBW_ 8 | 92 #endif 93 AT91_ SMC_ TDF_( 3)); 94 / / peripheral clock on register parallel IO controller C 95 at91_ sys_ write(AT91_ PMC_ PCER, 1 << AT91SAM9G45_ ID_ PIOC); 96 97 / * configure RDY / BSY * / 98 / / enter initialization 99 at91_ set_ gpio_ input(AT91_ PIN_ PC8, 1); 100 101 / * enable nandflash * / 102 / / output initialization 103 at91_ set_ gpio_ output(AT91_ PIN_ PC14, 1); 104 }105 #endif106 107 #ifdef CONFIG_ HAS_ DATAFLASH108 staTIc void at91samm10g45ek_ spi_ hw_ init(void)109 {
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