"I. parasitic capacitance of via
The via itself has parasitic capacitance to the ground. If it is known that the diameter of the isolation hole of the via on the floor is D2, the diameter of the via pad is D1, the thickness of the PCB is t, and the dielectric constant of the substrate is ε， The parasitic capacitance of the via is approximately:
C=1.41 ε TD1/（D2-D1）
The parasitic capacitance of the via will mainly affect the circuit by prolonging the rise time of the signal and reducing the speed of the circuit. For example, for a PCB board with a thickness of 50mil, if a via with an inner diameter of 10mil and a pad diameter of 20MIL is used, and the distance between the pad and the floor copper area is 32mil, we can approximately calculate the parasitic capacitance of the via through the above formula: C = 1.41x4.4x0.050x0.020 / (0.032-0.020) = 0.517pf, The rise time variation caused by this part of capacitance is: t10-90 = 2.2c (Z0 / 2) = 2.2x0.517x (55 / 2) = 31.28ps. It can be seen from these values that although the effect of the rise delay caused by the parasitic capacitance of a single via is not very obvious, the designer should carefully consider if vias are used for inter layer switching for many times in routing.
2、 Parasitic inductance of via
Similarly, there is parasitic inductance as well as parasitic capacitance in vias. In the design of high-speed digital circuits, the harm caused by parasitic inductance of vias is often greater than that of parasitic capacitance. Its parasitic series inductance will weaken the contribution of bypass capacitance and the filtering effect of the whole power supply system. We can simply calculate the parasitic inductance of a via approximation with the following formula:
L = 5.08h [ln (4h / D) + 1], where l refers to the inductance of the via, h is the length of the via, and D is the diameter of the central borehole. It can be seen from the formula that the diameter of the via has little influence on the inductance, while the length of the via has the greatest influence on the inductance. Still using the above example, it can be calculated that the inductance of the via is: l = 5.08x0.050 [ln (4x0.050 / 0.010) + 1] = 1.015nh. If the rise time of the signal is 1ns, the equivalent impedance is XL = π L / t10-90 = 3.19 Ω. Such impedance cannot be ignored when there is high-frequency current. In particular, it should be noted that the bypass capacitor needs to pass through two vias when connecting the power supply layer and the stratum, so that the parasitic inductance of the vias will be doubled.
3、 Via design in high speed PCB
Through the above analysis of via parasitic characteristics, we can see that in high-speed PCB design, seemingly simple vias often bring great negative effects to circuit design. In order to reduce the adverse impact caused by the parasitic effect of vias, the following can be achieved as far as possible in the design:
1. Considering the cost and signal quality, a reasonable via size is selected. For example, for the interior of floors 6-10)
For memory module PCB design, it is better to select 10 / 20MIL (drilling / pad) vias. For some high-density small-size boards, you can also try to use 8 / 18mil vias. Under the current technical conditions, it is difficult to use smaller vias. For vias of power supply or ground wire, larger size can be considered to reduce impedance.
2. From the two formulas discussed above, it can be concluded that the use of thinner PCB is beneficial to reduce the two parasitic parameters of vias
3. The signal routing on the PCB board shall not change layers as far as possible, that is, unnecessary vias shall not be used as far as possible.
4. The pins of the power supply and ground should be perforated nearby. The shorter the lead between the via and the pin, the better, because they will‘
This leads to an increase in inductance. At the same time, the leads of power supply and ground shall be as thick as possible to reduce impedance.
5. Place some grounded vias near the vias of signal layer change to provide the nearest circuit for the signal. Even a large number of redundant grounding vias can be placed on the PCB. Of course, it also needs to be flexible in design. The via model discussed above is that there are pads in each layer. Sometimes, we can reduce or even remove the pads in some layers. Especially when the via density is very large, it may lead to the formation of a cut-off groove in the copper layer. To solve this problem, in addition to moving the location of the via, we can also consider reducing the pad size of the via in the copper layer.
Q: why can't symbols copied from word files be displayed normally in Protel
Answer: are you in Sch environment or PCB environment? In PCB environment, some special characters cannot be displayed because words are reserved at that time.
Q: net has the same name as port. Can I connect to PCB
Answer: Yes, PROTEL can generate networks in many ways. When you use port port in the hierarchy diagram, each circuit diagram can use the same net name, and they will not be connected because the network name is the same. But please do not use the power port because it is global.
Q: Why did the pad attribute change when importing pads file in Protel99SE
Answer: This is mostly caused by the differences between the two software versions and each version. Usually, it's OK to make manual adjustment.
Q: Excuse me, prawn Yang: why can't you modify the properties in Protel after converting the schematic diagram of power logic into Protel through software? As long as you modify it, it's either unrealistic or full display properties? thank you!
Complex: if full display, you can make a global edit to display only the desired part.
Q: what are the principles of copper laying?
Re: laying copper should generally be more than twice your safety distance. This is the general knowledge of layout. " d： W4 k： b# W* G5 i） E
Q: is there any improvement in automatic layout of potel DXP? When importing packages, can they be automatically arranged according to the layout of the schematic diagram# b“ _ 1 n3 q7 J- V（ Q8 N： w
Complex: PCB layout and schematic layout have no certain internal inevitable relationship. Therefore, potel DXP will not be automatically arranged according to the schematic layout during automatic layout（ The component class established according to the sub diagram can help the PCB layout (according to the connection of the schematic diagram).
Q: where can I buy the data of signal integrity analysis
Reply: Protel software is equipped with a detailed signal integrity analysis manual.
Q: why is copper laid? What is the size of the file? What is the method?
Re: the amount of copper laying data is large, which is understandable. However, if it is too large, your setting may not be scientific.
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Q: is there any way to scale the graphic symbols of the schematic diagram?
Reply: No.
Q: Protel simulation can demonstrate the principle. If there is a detailed model, good results can be obtained
Complex: Protel simulation is fully compatible with spice model. You can obtain free SPICE model from device manufacturers for simulation. Protel also provides modeling methods, has professional simulation knowledge, and can establish effective models.
Q: how to add Chinese characters to 99SE? If there are many things missing after Sinicization! 3-28 14:17:0, but it does lack a lot of functions!
Fu: maybe the Chinese version is wrong.
Q: how to make a pad with a hole of 2 * 4mm and an outer diameter of 6mm?
Re: mark the square hole size on the mechanical layer. Communicate specific requirements with plate manufacturers.
Q: I know, but how does the inner layer connect the power and ground to the inner layer. There is no network table. If there is a network table, there will be no problem. 4 x * ^! S. c/ {
Complex: use the from to class to generate network connections
Q: how to make elliptical pads in 99SE? The method of placing continuous pads is not desirable, and the circuit board manufacturer is not happy. Can I add this setting in the next version?
Complex: when building library components, you can use non pad pixels to form the desired pad shape. When designing PCB, make it have the same network attributes. We can advise Protel.
Q: how to get the previous schematic library and PCB library for free
Re: you can download it from www.protel.com
Q: just now I mentioned how to write hollow (not covered with copper) words on copper cladding. The expert replied to write first, then cover with copper, and then remove the words in the book, but I tried. After deleting the words, they were not empty and covered with copper. Did the expert make a mistake? Can you try
Reply: the Chinese word must be placed by the method provided by Protel99SE, and then the Chinese (English) word shall be removed from the component (because it is a component), the safety spacing shall be set to 1mil, then copper coated, and then move the copper coated. The program will ask whether to re copper coated and answer No.
Q: how to the pin sequence of components when drawing schematic diagram?
Duplicate: when building the schematic library, it has a powerful check function, which can check the serial number, repetition, omission, etc. The array discharge function can also be used to place regular pins at one time.
Q: after protel99se6 automatic wiring, disordered wiring will appear near the pins of the integrated block, such as burr, sometimes even the triangle wiring, which needs to be corrected by a lot of manual. How can this problem be avoided?
Complex: reasonably set the component grid and optimize the routing again.
Q: after drawing with Protel and repeatedly modifying, it is found that the file volume is very large (virtual swelling), which is much smaller after exporting and then importing. Why? Is there any other way to lose weight for documents?
Fu: in fact, at that time, the copper laying of Protel was caused by the composition of lines. Due to the problem of intellectual property rights, the "irrigation" function in pads could not be used, but it had its advantage that "dead copper" could be automatically deleted. If the file is large, it will be small if you compress it with winzip. It will not affect your file sending.
Q: on the same wire, how to make different parts of it have different widths and appear continuous and beautiful? thank you!
Reply: it cannot be completed automatically, which can be realized by editing skills.
Liaohm asked: how to divide an arc?
Fanglin 163 reply: use conventional geometry knowledge. EDA is just a tool.
Q: the HDL used in Protel is an ordinary VHDL
Answer: Protel PLD is not, PROTEL FPGA is.
Q: after mending the tears, the copper is paved. Sometimes the grid will be incomplete. What should I do?
Re: that's because you set a thermal isolation belt when making up tears. You only need to pay attention to the safety distance and the mode of thermal isolation belt. It can also be repaired.
Q: can we make asymmetric pads? When you drag a route, the connected lines keep their original angle and drag together?
Complex: can be used as asymmetric pad. When you drag a route, the connected lines cannot be dragged together directly at the original angle.
Q: can Protel achieve the same effect as high-end EDA software when it reaches its full potential
Reply: depending on the design.
Q: can the automatic wiring effect of Protel DXP reach the level of the original accel?
Answer: there is more than that.
Q: Protel's PLD function doesn't seem to support the popular HDL language?
Reply: the CUPL language used by Protel PLD is also an HDL language. The next version can be input directly in VHDL language.
Q: what are the hardware requirements for the 3D function in PCB?
Complex: OpenGL. 1 needs to be supported
Q: how to quickly and intact the wiring of a physical hard plate into the computer?
Reply: the fastest way is to scan, then convert it into film file with bmp2pcb program, and then modify it, but your PCB accuracy must be more than 0.2mm. Bmp2pcb program can be downloaded on 21IC. Your circuit board must be sandpaper and very bright to succeed.
Q: how to define a network name for a circuit contact when drawing a PCB directly?
Duplicate: set in the net edit dialog box.)
Q: how to make the aperture display or symbol mark in the data, the same as Allego
Complex: there are options in the output, which can generate borehole statistics and various aperture symbols.
Q: the locking function of automatic wiring is not easy to use. Some systems will be re deployed. I don't know what's going on?
Reply: the latest version has no such problems.
Q: how to realize the overall turnover of multiple original devices
Duplicate: select the component to flip at one time.
Q: the P 99 version I use crashes when Chinese characters are added. What is the reason?
Reply: it should be caused by version D.
Q: how to open the file of powpcb with Protel?
Re: first create a new PCB file, and then use the import function to achieve.
Q: how do I import Gerber files from Protel99
Reply: Protel PCB can only import its own Gerber, while Protel cam can import Gerber in other formats
Q: how to change the thin line of PCB routing into thick line
Duplicate: double click Modify + global edit. Pay attention to the matching conditions. Modify the rule to fit the new lineweight.
Q: how to modify the pad size in an IC package? How to set the global modification?
Duplicate: select all for global editing
Q: how to modify the pad size in an IC package?
Re: modify the pad size in an integrated circuit package in the library. As we all know, it can also be modified on a PCB（ Unlock in component properties first)
Q: can some parts of component symbols be modified or deleted when making PCB?
Complex: remove the component lock in the component attribute to edit the component in the PCB without affecting the components in the library.
Q: the pad is a ground wire. How to set the width of the connecting line between the pad and the ground after wrapping the ground
Re: set the connection mode with the pad before grounding
Q: why is 99SE stored in the project format?, Read the full text“
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